Thursday, IBM introduced a breakthrough in built-in circuit design—the world’s first 2 nanometer course of. IBM says its new course of can produce CPUs able to both 45 % increased efficiency, or 75 % decrease power use than fashionable 7 nm designs.
If you happen to’ve adopted latest processor information, you are seemingly conscious that Intel’s present desktop processors are nonetheless laboring alongside at 14 nm, whereas the corporate struggles to finish a migration downward to 10 nm—and that its rivals are on a lot smaller processes, with the smallest manufacturing chips being Apple’s new M1 processors at 5 nm. What’s much less clear is strictly what which means within the first place.
Initially, course of dimension referred to the literal two-dimensional dimension of a transistor on the wafer itself—however fashionable 3D chip fabrication processes have made a hash of that. Foundries nonetheless check with a course of dimension in nanometers, but it surely’s a “2D equal metric” solely loosely coupled to actuality, and its true that means varies from one fabricator to the subsequent.
To get a greater thought of how IBM’s new 2 nm course of stacks up, we are able to check out transistor densities—with manufacturing course of data sourced from Wikichip and knowledge on IBM’s course of courtesy of Anandtech’s Dr. Ian Cutress, who obtained IBM to translate “the scale of a fingernail”—sufficient space to pack in 50 billion transistors utilizing the brand new course of into 150 sq. millimeters.
|Producer||Instance||Course of Dimension||Peak Transistor Density (thousands and thousands/sq mm)|
|Intel||Cypress Cove (desktop) CPUs||14 nm||45|
|Intel||Willow Cove (laptop computer) CPUs||10 nm||100|
|AMD (TSMC)||Zen 3 CPUs||7 nm||91|
|Apple (TSMC)||M1 CPUs||5 nm||171|
|Apple (TSMC)||next-gen Apple CPUs, circa 2022||3 nm||~292 (estimated)|
|IBM||Could 6 prototype IC||2 nm||333|
As you may see within the chart above, the easy “nanometer” metric varies fairly strenuously from one foundry to the subsequent—particularly, Intel’s processes sport a a lot increased transistor density than implied by the “course of dimension” metric, with its 10 nm Willow Cove CPUs being roughly on par with 7 nm components coming from TSMC’s foundries. (TSMC builds processors for AMD, Apple, and different high-profile clients.)
Though IBM claims that the brand new course of may “quadruple mobile phone battery life, solely requiring customers to cost their units each 4 days,” it is nonetheless far too early to ascribe concrete energy and efficiency traits to chips designed on the brand new course of. Evaluating transistor densities to present processes additionally appears to take among the wind from IBM’s sails—evaluating the brand new design to TSMC 7 nm is effectively and good, however TSMC’s 5 nm course of is already in manufacturing, and its 3 nm course of—with a really related transistor density—is on monitor for manufacturing standing subsequent yr.
We do not but have any bulletins of actual merchandise in improvement on the brand new course of. Nevertheless, IBM at present has working partnerships with each Samsung and Intel, who would possibly combine this course of into their very own future manufacturing.
Itemizing picture by IBM